Kamal Raj - Hardware Security Researcher

About Me

Hi, I’m Kamal Raj, a Research Associate at TUMCREATE Singapore. I specialize in hardware security, focusing on developing hardware accelerator architectures for Post-Quantum Cryptography (PQC) and designing countermeasures against side-channel attacks. My work aims to keep everything from tiny IoT sensors to massive cloud servers secure in a post-quantum era.

Before joining TUMCREATE, I worked as a Research Associate at Nanyang Technological University (NTU), developing area-efficient hardware implementations for various PQC schemes while handling both the design and experimental validation of lightweight side-channel analysis countermeasures.

I hold an M.Tech. degree in VLSI from the Indian Institute of Technology Mandi (2023), where my research focused on optimizing the hardware footprint of the ASCON cipher and developing lightweight authentication protocols.

Originally from the Himalayan village of Nesang, I am driven by a passion to build a foundation of trust in the hardware that powers our digital world. When I’m not optimizing RTL, I enjoy capturing the world through my camera lens, trekking, or mentoring the next generation of hardware engineers.

Research Interests

Key focus areas across cryptographic engineering, physical security, and open-source silicon.

PQC Hardware Acceleration

Architecting area-efficient and high-throughput RTL engines for NIST-standardized Post-Quantum Cryptography schemes on ASIC and FPGA.

ML-DSA HQC RTL / FPGA

Side-Channel Protection

Developing low-overhead higher-order algorithmic masking countermeasures and power/EM leakage protections integrated directly into RTL pipelines.

Masking SCA Security TVLA

Open Silicon & IP Cores

Creating reusable, open-source SystemVerilog cryptographic coprocessors and hardware IP cores for community benchmark and security evaluation.

Open Silicon SystemVerilog IP Cores

Lightweight IoT Cryptography

Optimizing hardware footprints for lightweight ciphers like ASCON and low-overhead hardware authentication protocols for constrained IoT nodes.

ASCON IoMT Low-Area Logic

PUFs & Roots-of-Trust

Designing and evaluating silicon Physical Unclonable Functions (PUFs) for secure device key generation, hardware fingerprinting, and mutual authentication.

PUF Root-of-Trust Auth