KAMAL RAJ

Professional Summary

Highly specialized Hardware Security Architect with an M.Tech from IIT Mandi and 2.5+ years of experience in architecting NIST-standardized Post-Quantum Cryptographic (PQC) IP. Expert in developing area-optimized architectures for ML-DSA and HQC PQC schemes with robust 1st-order masking countermeasures. Proven track record in automated FPGA sign-off flows and FPGA-based side-channel evaluation (SCA).

Technical Skills

• Architectures & Standards: NIST PQC (FIPS 204 ML-DSA, FIPS 205 ML-KEM), HQC, ASCON, AES, FIPS PUB 202.
• Hardware Security: Side-Channel Analysis (SCA), Fault Injection Analysis (FIA), Countermeasure Design, TVLA Evaluation.
• Hardware Platforms: SAKURA-X (SCA Evaluation Board), Xilinx Artix-7, Zynq-7000, UltraScale+.
• FPGA/ASIC Design: SystemVerilog, Verilog, RTL Micro-architecture, PPA Optimization, Linting, CDC/RDC.
• Tools: Vivado, Verilator, Yosys, OpenROAD, Git.
• Languages: Python (Automation), Tcl (Scripting), SystemVerilog, C/C++.

Professional Experience

• Lead IP Maintainer: Managed centralized RTL repositories for PQC hardware cores; established modular coding standards and developed an automated CI/CD pipeline for Known Answer Testing (KAT) to ensure multi-project re-usability.
• RTL Design & Sign-off: Architected high-speed and area-optimized hardware accelerators for NIST-standard PQC algorithms with a focus on CDC/RDC/Lint cleanliness using Verilator for industrial-grade sign-off.
• SCA Protection: Implemented hardware-level countermeasures (masking/shuffling) to mitigate Power Analysis attacks in ML-DSA hardware cores; evaluated leakage profiles on SAKURA-X FPGA platforms using TVLA.
• Flow Automation: Developed Python and Tcl scripts to automate the synthesis-to-bitstream flow, ensuring 100% reproducible results and timing closure across different technology nodes.

Key Projects

• Developed a low-area, side-channel resistant architecture for the HQC algorithm, optimizing modular arithmetic for resource-constrained FPGA environments.

• Designed and implemented a 1st-order masking countermeasure to protect ML-DSA hardware against Differential Power Analysis (DPA) attacks.

• Developed a Physical Unclonable Function (PUF) based protocol providing lightweight mutual authentication for IoT nodes, eliminating static key storage.

• Engineered a high-efficiency architecture for the ASCON authenticated encryption cipher, optimized for LUT/FF footprint on Artix-7 FPGAs.

Publications

Peer-Reviewed Journals & Conferences

• Kamal Raj, S. Bodapati, and A. Chattopadhyay, "PUF-Based Lightweight Mutual Authentication Protocol for Internet of Things (IoT) Devices," 2024 IEEE ISCAS, Singapore.
  DOI: 10.1109/ISCAS58744.2024.10558672
• Kamal Raj and S. Bodapati, "FPGA Based Light Weight Encryption of Medical Data for IoMT Devices using ASCON Cipher," 2022 IEEE iSES, India.
  DOI: 10.1109/iSES54909.2022.00048

Under Review & Preprints

• Kamal Raj, P. Ravi, T.K. Chia, and A. Chattopadhyay, "Improved ML-DSA Hardware Implementation With First Order Masking Countermeasure."
  URL: https://eprint.iacr.org/2024/1817

Professional Services

• Reviewer, IEEE Transactions on Circuits and Systems II (TCAS-II)
• Reviewer, IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems (TCAD)

Education