KAMAL RAJ

Professional Summary

Hardware Security Researcher with an M.Tech in VLSI from IIT Mandi and 2.5+ years of specialized experience designing, optimizing, and securing Post-Quantum Cryptographic (PQC) Hardware IPs. Proven track record in architecting side-channel attack (SCA) protected architectures for ML-DSA and HQC algorithms utilizing robust 1st-order masking countermeasures. Expert in FPGA prototyping, and navigating complex micro-architectural trade-offs between performance and side-channel resilience to deliver production-grade, verification-clean silicon IPs.

Technical Skills

• VLSI Design: RTL Design, FPGA Prototyping, ASIC Synthesis, Static Timing Analysis (STA), Place & Route (PnR).
• EDA Tools: Vivado, iVerilog, Verilator, Yosys, OpenROAD, OpenSTA, KLayout.
• Hardware Platforms: Artix-7, Zynq-7000, Kintex-7, SAKURA-X (SCA Evaluation Board).
• Languages: Verilog HDL, Python (Automation), C/C++, Makefile scripting.
• Cryptographic IPs: PQC (ML-DSA, HQC, MAYO), AES, SHA3, ASCON.
• Hardware Security: SCA Countermeasures (1st-Order Masking, Noise Injection/Hiding), Physical Unclonable Functions (PUFs).

Professional Experience

• NIST-Standard PQC Accelerator Design: Architected, designed, and implemented high-throughput, area-efficient hardware accelerators for ML-DSA (Dilithium) and HQC algorithms. Prototyped and validated RTL across AMD Xilinx Artix-7, Zynq-7000, and Kintex-7 FPGA platforms.
• Side-Channel-Aware Microarchitecture: Conducted extensive microarchitectural exploration to navigate the critical engineering trade-offs between high-performance execution and the severe area/timing overheads introduced by side-channel countermeasures.
• Countermeasure Implementation: Developed and integrated modular 1st-order masking and noise-injection techniques to secure the ML-DSA pipeline against Differential Power Analysis (DPA/CPA). Successfully optimized randomized share distribution to drastically limit latency inflation.
• Resource-Reuse Optimization: Strategically minimized the silicon and power footprint of HQC side-channel protections by engineering resource-reuse techniques, sharing heavy hardware blocks between base cryptographic operations and countermeasure logic.
• Physical Leakage Evaluation: Evaluated physical leakage profiles using Test Vector Leakage Assessment (TVLA) methodologies on specialized SAKURA-X FPGA side-channel analysis boards.
• HW/SW Co-Verification & Automation: Built automated Python and Makefile testing infrastructure to execute rigorous Known Answer Tests (KAT), co-verifying custom hardware accelerator execution against software cryptographic reference implementations.
• ASIC-Oriented Quality & Sign-off: Enforced strict lint-cleanliness and semantic verification using Verilator. Managed synthesis, Static Timing Analysis (STA), and optimization flows to ensure a seamless transition toward manufacturable ASIC designs.
• Lead IP Repository Maintainer: Owned and scaled the centralized RTL repository for PQC hardware cores. Established modular coding standards and unified interface protocols to maximize multi-project re-usability and ease SoC integration.

• Designed IIoT solutions for industrial monitoring; developed an automated remote test fixture for high-current (500A) relay testing that replaced manual measurement with sensor-driven data logging and cloud integration.

Publications

Peer-Reviewed Journals & Conferences

• Kamal Raj, P. Ravi, T.K. Chia, and A. Chattopadhyay, "Improved ML-DSA Hardware Implementation With First Order Masking Countermeasure," Journal of Hardware and Systems Security (HaSS).
  DOI: 10.1007/s41635-026-00183-3
• Kamal Raj, P. Gan, and A. Chattopadhyay, "A Configurable HQC Hardware Architecture via Soft-Modular Logic and Fixed Memory Structures," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2026 (Accepted/To appear).
• Kamal Raj, S. Bodapati, and A. Chattopadhyay, "PUF-Based Lightweight Mutual Authentication Protocol for Internet of Things (IoT) Devices," 2024 IEEE ISCAS, Singapore, 2024, pp. 1-5.
  DOI: 10.1109/ISCAS58744.2024.10558672
• Kamal Raj and S. Bodapati, "FPGA Based Light Weight Encryption of Medical Data for IoMT Devices using ASCON Cipher," 2022 IEEE iSES, Warangal, India, 2022, pp. 196-201.
  DOI: 10.1109/iSES54909.2022.00048

Preprints

• P. Gan, P. Ravi, Kamal Raj, A. Baksi, and A. Chattopadhyay, "Classic McEliece Hardware Implementation with Enhanced Side-Channel and Fault Resistance," TechRxiv Preprint.
  Link: https://www.techrxiv.org/doi/full/10.36227/techrxiv.171925242.26878384
• R. Choudhary, S. Bodapati, Kamal Raj, and A. Chattopadhyay, "ASCON-KECCAK AEAD: A Novel Hardware Architecture for Cryptographic Processing," TechRxiv Preprint.
  DOI: https://doi.org/10.36227/techrxiv.174831454.40989725/v2

PROFESSIONAL SERVICE & ACTIVITIES

Invited Journal Reviewer

• IEEE Transactions on Circuits and Systems II (TCAS-II)
• IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems (TCAD)
• ACM Transactions on Embedded Computing Systems (TECS)

Academic Leadership & Mentorship

• Academic Leadership: Served as a Graduate Teaching Assistant for Cyber-Physical System Security, Computer Organization, and Digital System Design at NTU and IIT Mandi.
• Mentorship: Mentored Master’s and undergraduate students in hardware security architectures, RTL design, and digital system verification methodologies.
• Community Engagement: Technical Volunteer and Assistant for IEEE workshops and university-led academic seminars.

Education